1. Field of the Invention
The present invention relates to a high frequency amplifier circuit which is provided in a high frequency circuit section of a transmitting section of a mobile communication terminal so as to amplify a high frequency signal. The invention further relates to a mobile communication terminal using the high frequency amplifier circuit. The circuit addressed in the invention is such a high frequency amplifier circuit that the output power thereof is controlled by a control voltage.
2. Related Art of the Invention
Recently, in the field of mobile communication, combined portable telephone terminals where a plurality of communication schemes are integrated are entering into the mainstream of mobile communication terminals. An example of this is a mobile communication terminal that supports both PDC (Personal Digital Cellular) and W-CDMA (Wide band Code Division Multiple Access) schemes. Such a combined mobile communication terminal permit the use of the advantages in the respective schemes, such as the wideness of a service area in PDC and a high data communication rate in W-CDMA, and hence are expected to spread more rapidly in the future.
In such a combined mobile communication terminal, the PDC and W-CDMA schemes use carrier frequencies different from each other. Thus, two high frequency circuit blocks respectively for PDC and W-CDMA are necessary in the terminal. Further, for the purpose of size reduction in the mobile communication terminal, much attention is focused on the reduction in the number of components on the mobile communication terminal board and on the resulting size reduction in the high frequency circuit blocks.
Described below is a typical example of a prior art portable telephone terminal which supports a plurality of communication schemes such as PDC and W-CDMA.
FIG. 8 is a block diagram showing the configuration of a radio section of a typical example of a prior art portable telephone terminal. In FIG. 8, the radio section of the mobile communication terminal comprises a transmitting section 200, a receiving section 400, a synthesizer section 410, and a shared device section 500.
The transmitting section 200 comprises: an up converter 201 for converting an intermediate frequency modulation signal, that is, a modulation signal input having an intermediate frequency such as 600 MHz, into a transmission frequency signal; a variable gain high frequency amplifier circuit 202 for amplifying the output signal of the up converter 901 from 1 mW or lower into 10 mW or the like at maximum; a high frequency switch 203 for switching band pass filters to be used depending on the transmission frequency, that is, for switching the signal path; band pass filters 204 and 207 each for extracting a signal in one of two transmission bands; a high power high frequency amplifier circuit 205 having a fixed gain so as to amplify the high frequency signal output of the band pass filter 204 from 10 mW or lower into 1 W or the like at maximum; an isolator 206 for providing the output of the high power high frequency amplifier circuit 205 to the shared device section 500; a high power high frequency amplifier circuit 208 having a fixed gain so as to amplify the high frequency signal output of the band pass filter 207 from 10 mW or lower into 1 W or the like at maximum; and an isolator 209 for providing the output of the high power high frequency amplifier circuit 208 to the shared device section 500. The above-mentioned transmission frequency is approximately 900 MHz in PDC and approximately 1.9 GHz in W-CDMA.
The receiving section 400 comprises: a front end IC 401 for amplifying the reception signal received in the shared device section 500 and then mixing this reception signal with a local oscillation signal provided from the synthesizer section 410; and a band pass filter 402 for extracting an intermediate frequency signal from the output signal of the front end IC 401.
The synthesizer section 410 comprises a temperature compensated crystal oscillator (TCXO) 411, a phase locked loop (PLL) circuit 412, and a voltage controlled oscillator (VCO) 413.
The shared device section 500 comprises antennas 501 and 502 and a duplexer 503.
In order that a plurality of communication schemes such as PDC and W-CDMA are supported and that the overall high frequency circuit block of the mobile communication terminal is miniaturized, the up converter 201 and the high frequency amplifier circuit 202 are shared. Nevertheless, as for the band pass filters 204 and 207, the high power high frequency amplifier circuits 205 and 208, and the isolators 206 and 209, these circuit blocks need to be provided in correspondence to the respective communication frequencies. Further, the high frequency switch 203 is necessary for selecting circuit blocks corresponding to the communication frequency.
FIG. 9 is a block diagram of the radio section of the typical example of a prior art portable telephone terminal shown in FIG. 8. That is, FIG. 9 is a block diagram showing detailed configuration of the transmitting section 200 and the shared device section 500.
In FIG. 9, an intermediate frequency modulation signal generated by modulating a voice signal or the like is inputted to a signal input terminal 101. The up converter 103 receives through the signal input terminal 10 the intermediate frequency modulation signal generated by modulating a voice signal or the like, and at the same time receives a local oscillation signal from an oscillator 102 so as to convert the intermediate frequency signal into a transmission frequency signal. More specifically, the up converter 103 mixes the signal having the intermediate frequency (the intermediate frequency modulation signal) with the local oscillation signal provided from the oscillator 102 so as to convert the intermediate frequency signal into the transmission frequency signal.
Here, the frequency of the intermediate frequency modulation signal inputted to the up converter 103 is denoted by fif. The local oscillation frequency of the oscillator 102 is denoted by flo. The frequency of the transmission signal is denoted by fc. Then, the frequency fc of the transmission signal is expressed by the following equation, and is outputted as a frequency fc from the up converter 103.fc=flo±fif 
When the oscillation frequency of the oscillator 102 is adjusted, transmission waves can be synthesized in correspondence to a plurality of transmission frequencies for the PDC and W-CDMA schemes or the like.
A high frequency amplifier circuit 104 is provided with a gain control function, and amplifies the signal having the transmission frequency into 10 mW or the like at maximum. A high frequency switch 105 is used for selecting high frequency circuits corresponding to the communication frequency.
In the PDC scheme, a band pass filter 106, a high power high frequency amplifier circuit 107, and an isolator 108 are used as the above-mentioned high frequency circuits. In the W-CDMA scheme, a band pass filter 109, a high power high frequency amplifier circuit 110, and an isolator 111 are used as the above-mentioned high frequency circuits.
In the PDC scheme, the output signal of the high frequency amplifier circuit 104 is transmitted from a terminal 105a of the high frequency switch 105 to a terminal 105b thereof so as to be inputted to the band pass filter 106. From the signal Inputted to the band pass filter 106, the band pass filter 106 extracts a signal in the transmission band. Then, the signal is outputted from the band pass filter 106. The high power high frequency amplifier circuit 107 amplifies the output signal of the band pass filter 106, which is a signal having the transmission frequency, into 1 W or the like at maximum. The output of the high power high frequency amplifier circuit 107 is provided through the isolator 108 to a terminal 112a of a duplexer 112.
In the W-CDMA scheme, the output signal of the high frequency amplifier circuit 104 is transmitted from a terminal 105a of the high frequency switch 105 to a terminal 105c thereof so as to be inputted to the band pass filter 109. From the signal inputted to the band pass filter 109, the hand pass filter 109 extracts a signal in the transmission band. Then, the signal is outputted from the bandpass filter 109. The high power high frequency amplifier circuit 110 amplifies the output signal of the band pass filter 109, which is a signal having the transmission frequency, into 1 W or the like at maximum. The output of the high power high frequency amplifier circuit 110 is provided through the isolator 111 to a terminal 112b of the duplexer 112.
The duplexer 112 has the functions of: transmitting to an antenna 113 the transmission signal outputted from the isolator 108; transmitting to a signal output terminal 115 a reception signal received in the antenna 113; transmitting to an antenna 114 the transmission signal outputted from the isolator 111; and transmitting to a signal output terminal 116 a reception signal received in the antenna 114.
As such, in the high frequency circuit block of FIG. 9, the antennas are used selectively depending on the communication schemes. That is, the antenna 113 is used in the PDC scheme, while the antenna 114 is used in the W-CDMA scheme.
More specifically, the duplexer 112 has the functions of: passing the signal in the direction from the terminal 112a to the terminal 112c; blocking the signal in the directions from the terminal 112a to the terminals 112b, 112d, 112e, and 112f; passing the signal in the direction from the terminal 112b to the terminal 112d; blocking the signal in the directions from the terminal 112b to the terminals 112a, 112c, 112e, and 112f; passing the signal in the direction from the terminal 112c to the terminal 112e; blocking the signal in the directions from the terminal 112c to the terminals 112a, 112b, 112d, and 112; passing the signal in the direction from the terminal 112d to the terminal 112f; blocking the signal in the directions from the terminal 112d to the terminals 112a, 112b, 112c, and 112e; blocking the signal in the directions from the terminal 112e to the terminals 112a, 112b, 112c, 112d, and 112f; and blocking the signal in the directions from the terminal 112f to the terminals 112a, 112b, 112c, 112d, and 112e. 
The prior art portable telephone terminal has used the configuration of FIG. 9, so that the high frequency circuit blocks are miniaturized in a communication terminal in which the high frequency switch 105 selects a high frequency circuit so as to support a plurality of communication schemes.
Described next is a high frequency amplifier circuit which supports a plurality of communication schemes such as PDC and W-CDMA. FIG. 10 is a detailed circuit block diagram showing the high frequency amplifier circuit 104 of FIG. 9.
As shown in FIG. 10, in the high frequency amplifier circuit 104, a high frequency signal inputted through a signal input terminal 181 is provided to a gain control circuit 183 via an impedance matching circuit 182 for impedance transformation. The output signal of the gain control circuit 183 is provided to and amplified by an amplifier 184. The output signal of the amplifier 184 is provided to and amplified by an amplifier 186 via an impedance matching circuit 185 for impedance transformation. The output signal of the amplifier 186 is transmitted to a signal output terminal 188 via an impedance matching circuit 187 for impedance transformation.
Described below is the gain control operation using the high frequency amplifier circuit 104. The amount of attenuation in the gain control circuit of the high frequency amplifier circuit 104 is controlled by the setting of the voltage value on a control terminal 189. The voltage on the control terminal 189 is controlled using a D/A converter. The D/A converter sets this voltage on the control terminal 189 in response to a control signal from a controlling section.
FIG. 11 shows the relation between the control voltage and the output power in the above-mentioned high frequency amplifier circuit 104 of FIG. 9. Here, the input power to the high frequency amplifier circuit 104 is maintained at constant. As seen from FIG. 11, the output power of the high frequency amplifier circuit of FIG. 9 varies depending on the change in the control voltage. When the high frequency amplifier circuit 104 is used as the transmission block in the radio section of the mobile communication terminal of FIG. 8, this circuit permits output power control for the transmission power of the mobile communication terminal.
Described below is the gain control circuit used in the high frequency circuit block of the mobile communication terminal.
The gain control circuit in the high frequency circuit block is constructed from field effect transistors (FETs, hereafter). That is, in the prior art, FETs have been used as variable resistors, so as to implement the gain control circuit.
An example of such a prior art gain control circuit is described in JP-A-H09-135102 (page 5 and FIGS. 1 and 2).
FIG. 12 shows a prior art gain control circuit described in this JP-A-H09-135102. In FIG. 12, numeral 1 indicates a first FET. Numeral 2 indicates a second FET. Numeral 3 indicates a third FET. Numeral 4a indicates a first resistor connected in series to the first FET 1. Numeral 4b indicates a second resistor connected in series to the second FET 2. Numeral 4c indicates a third resistor connected in parallel to the third FET 3. Numeral 5 indicates the ground. Numeral 6a indicates an input terminal. Numeral 6b indicates an output terminal. Numeral 7a indicates a first series circuit. Numeral 7b indicates a second series circuit.
The operation of the gain control circuit is described below with reference to FIG. 12. When the voltage applied on the gate terminal of an FET is controlled, the FET is controlled between its ON and OFF states. When the FET is ON, the FET has a low impedance, and passes a signal. When the FET is OFF, the FET has a high impedance, and blocks a signal component.
Thus, when the first FET 1 and the second FET 2 are OFF and when the third FET 3 is ON, in an equivalent circuit to the gain control circuit, the first FET 1 and the second FET 2 serve as open ends relative to the input 6a and the output 6b, while the third FET 3 serves as a sufficiently small resistance. This equivalent circuit is shown in FIG. 13A. The circuit serves as a passage circuit.
When the first FET 1 and the second FET 2 are ON and when the third FET 3 is OFF, in an equivalent circuit to the gain control circuit, the first FET 1 and the second FET 2 serve as resistance components, while the third FET 3 has a high impedance and is open. This equivalent circuit is shown in FIG. 13B. The circuit is a n-type attenuator composed of the first resistor 4a, the second resistor 4b, and the third resistor 4c. 
In the prior art, the gain control circuit has been implemented by such circuit configuration.
A first problem is that in the gain control circuit according to the prior art, two kinds of control signals are necessary for controlling the gain control circuit, and hence causes complexity in the control circuit.
This is because a control voltage needs to be provided to the gate terminals of the first FET 1 and the second FET 2 constituting the gain control circuit, and because another control voltage needs to be provided to the gate terminal of the third FET 3 also constituting the gain control circuit. Thus, D/A converters for converting a control signal for gain control into analog signals are necessary for the respective gate terminals. This increases the circuits size of the high frequency circuit block.
A second problem is that in the gain control circuit according to the prior art, the gain control circuit can merely take two states having a low impedance and a high impedance.
This is because the voltage provided to the gate terminals of the first FET 1 and the second FET 2 constituting the gain control circuit and the other voltage provided to the gate terminal of the third FET 3 also constituting the gain control circuit are controlled individually, so that the FETs 1-3 are switched between ON and OFF, so that the gain control is achieved. That is, in the low impedance state, the first FET 1 and the second FET 2 are set OFF, while the third FET 3 is set ON. In the high impedance state, the first FET 1 and the second FET 2 are set ON and when the third FET 3 is set OFF. As such, the gain control is performed.
Thus, the amount of attenuation in the gain control circuit cannot take the other value than the two in the low impedance state and the high impedance state.
A third problem is that when a high frequency amplifier circuit supporting a plurality of communication schemes is constructed, the relation between the gain control voltage and the amount of attenuation in the gain control circuit varies depending on the communication scheme because of the frequency characteristics of the gain control circuit.
This is because the FETs constituting the gain control circuit have frequency characteristics, and hence the transmission characteristics between the source terminal and the drain terminal varies depending on the frequency.
A fourth problem is that when a gain control circuit used in a high frequency amplifier circuit supporting a plurality of communication schemes and having different frequencies depending on the communication schemes is constructed, a D/A converter connected to a control terminal needs a higher resolution in the output voltage in case that the control voltage and the gain control characteristics vary depending on the frequency.
This is because when a high frequency amplifier circuit supporting a plurality of communication schemes is constructed, the relation between the gain control voltage and the amount of attenuation in the gain control circuit varies depending on the communication scheme. Thus, the resolution of the D/A converter needs to be sufficiently high in correspondence to a communication scheme having the largest ratio of the amount of attenuation in the gain control circuit to the control voltage. This causes an increase in the circuit size of the D/A converter in the control circuit and in the number of the control parameters for the gain control voltage and the amount of attenuation used for controlling the gain control circuit. This causes complexity in the control circuit.